W3EG264M72AFSRXXXD3 ecc equivalent, 1gb - 2x64mx72 ddr sdram registered ecc.
Double-data-rate architecture DDR200, DDR266 and DDR333:
* JEDEC design specifications Phase-lock loop (PLL) clock driver to reduce loading Bi-directional data strobes.
* This product is under development, is not qualified or characterized and is subject to change or cancellation without .
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